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In this assignment, you will design and
synthesize the following designs using Xilinx Vivado:

  1. 32:1 multiplexer
    using four 8:1 and one 4:1 multiplexer
  2. 5-to-32
  3. A 4-bit
    wide computational unit according to the following function table:





 Output <= Input

No shift


Output <= Shift-left (Input)

Shift Left


Output <= Shift-right (Input)

Shift Right


Output <= 0

Zero output



For each
question above, submit vhdl code, RTL schematic, synthesis report, screenshots
of simulation waveforms, and test bench of the designs. Test your design using
at least five test cases. Mark two of the test cases and show the corresponding
inputs, expected outputs and simulated outputs for those two cases. The source
files should contain appropriate comments for better understanding. 

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